The general structures and manufacturing processes for electronic packages are described in, for example, Donald P. Seraphim, Ronald Lasky, and Che-Yo Li, Principles of Electronic Packaging, McGraw-Hill Book Company, New York, N.Y., (1988), and Rao R. Tummala and Eugene J. Rymaszewski, Microelectronic Packaging Handbook, Van Nostrand Reinhold, New York, N.Y. (1988), both of which are hereby incorporated herein by reference.
As described by Seraphim et al., and Tummala et al., an electronic circuit contains many individual electronic circuit components, e.g., thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form the circuits, and the individual circuits are further interconnected to form functional units. Power and signal distribution are done through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function, and the removal of thermal energy to remain functional. Microelectronic packages, such as, chips, modules, circuit cards, circuit boards, and combinations thereof, are used to protect, house, cool, and interconnect circuit components and circuits.
Within a single integrated circuit, circuit component to circuit component and circuit to circuit interconnection, heat dissipation, and mechanical protection are provided by an integrated circuit chip. This chip is referred to as the "zeroth" level of packaging, while the chip enclosed within its module is referred to as the first level of packaging.
There is at least one further level of packaging. The second level of packaging is the circuit card. A circuit card performs at least four functions. First, the circuit card is employed because the total required circuit or bit count to perform a desired function exceeds the bit count of the first level package, i.e., the chip. Second, the circuit card provides for signal interconnection with other circuit elements. Third, the second level package, i.e., the circuit card, provides a site for components that are not readily integrated into the first level package, i.e., the chip or module. These components include, e.g., capacitors, precision resistors, inductors, electromechanical switches, optical couplers, and the like. Fourth, the second level package provides for thermal management, i.e., heat dissipation.
Packages may be characterized by the material used as the dielectric, i.e., as ceramic packages or as polymeric packages. The basic process for polymer based composite package fabrication is described by George P. Schmitt, Bernd K. Appelt and Jeffrey T. Gotro, "Polymers and Polymer Based Composites for Electronic Applications" in Seraphim, Lasky, and Li, Principles of Electronic Packaging, pages 334-371, previously incorporated herein by reference, and by Donald P. Seraphim, Donald E. Barr, William T. Chen, George P. Schmitt, and Rao R. Tummala, "Printed Circuit Board Packaging" in Tummala and Rymaszewski, Microelectronics Packaging Handbook, pages 853-922, also previously incorporated herein by reference.
In the normal process for package fabrication a fibrous body, such as a non-woven mat or woven web, is impregnated with a resin. This step includes coating the fibrous body with an A- stage resin solution, evaporating the solvents associated with the resin, and partially curing the resin. The partially cured resin is called a B-stage resin. The body of fibrous material and B stage resin is called a prepreg. The prepreg, which is easily handled and stable, may be cut into sheets for subsequent processing.
Typical resins used to form the prepreg include epoxy resins, cyanate ester resins, polyimides, hydrocarbon based resins, and fluoropolymers.
For example, cyanate ester resins also used in forming prepregs. One type of cyanate ester resin includes dicyanates mixed with methylene dianiline bis-maleimide. This product may be further blended with compatible epoxides to yield a laminate material. One such laminate material is a 50:45:5 (parts by weight) of epoxy: cyanate: maleimide. Typical of cyanate ester resins useful in forming prepregs is the product of bisphenol-A dicyanate and epoxy, which polymerizes during lamination to form a crosslinked structure.
A still further class of materials useful in forming prepregs for rigid multilayer boards are thermosetting polyimides. While thermosetting polyimides exhibit high water absorption, and high cost, they have good thermal properties and desirable mechanical properties. The preferred polyimides for prepreg use are addition products such as polyimides based on low molecular weight bis-maleimides.
A closely related alternative package is flexible film packaging, also known as flex packaging. Flex packaging is described by Donald P. Seraphim, Donald E. Barr, William T. Chen, George P. Schmitt, and Rao R. Tummala, Printed Circuit Board Packaging, at pages 853-921, and especially pages 870-872 of R.R. Tummala and E. J. Rymaszewski, Microelectronics Packaging Handbook, previously incorporated herein by reference.
Flexible film packages are generally similar to pre-preg based circuit packages, however they are thinner then pre-preg based printed circuit boards, and are fabricated from polyimide or polyester rather than epoxy - glass fiber.
Surface circuitization of flex packages is accomplished by bonding copper foil with a suitable adhesive, as epoxy or acrylic, and photolithographically patterning the copper into circuit leads.
Subsequent processing of polymeric substrates includes circuitization, that is, the formation of a Cu signal pattern or power pattern on the prepreg or flex, or lamination of the prepreg to a power core. Circuitization may be additive or subtractive.
In the case of additive circuitization a thin film of an adhesion layer, such as a thin film of chromium, is first applied to the prepreg. The adhesion layer may be applied by sputtering. Typically, the film of adhesion metal is from about 500 Angstroms to about 2000 Angstroms. Thicker layers of chromium result in internal streses, while thinner layers may be non-continuous.
Thereafter a "seed" layer of copper is applied atop the adhesion layer. This copper layer is from about 3000 Angstroms thick to about 25,000 Angstroms (2.5 microns) thick. It may be applied by sputtering, electrodeposition, or electroless deposition.
Subsequently, photoresist is applied atop the copper "seed" layer, imaged, and developed to provide a pattern for circuit deposition. Copper circuitization is then plated onto the "seed" layer to provide the circuitization pattern on the surface of the package. The remaining photoresist is then stripped, leaving a thick copper plated circuitization pattern and a thin multilayer "background" of a "seed" copper- chromium adhesion layer.
The "seed" copper can be etched by various methods well known in the art. The chromium adhesion layer is removed, for example, by etching with, for example, permanganate etches and/or chloride etches. However, these etchants require careful cleaning steps to removed permanganate or chloride entrapped within crevices. Permanganate and hydrochloric acid so entrapped and/or entrained can result in loss of adhesion long after fabrication. This is especially so in the case of subsequent application of gold thin films atop the copper circuitization. The resulting circuitized prepreg is called a core.
The composite printed circuit package is fabricated by interleaving cores (including signal cores, signal/signal cores, power cores, power/power cores, and signal/power cores) with additional sheets of prepreg, and surface circuitization. Holes, as vias and through holes, may be drilled in individual core structures, for example, before or after circuitization, as described above, or in partially laminated modules.
An alternative package is Tape Automated Bonding (TAB). The TAB structure and process is described by Nicholas G. Koopman, Timothy C. Reiley, and Paul C. Totta, Chip To Package Interconnections, at pages 361-453, and especially pages 409-437 of R.R. Tummala and E. J. Rymaszewski, Microelectronics Packaging Handbook, previously incorporated herein by reference, and Charles G. Woychik and Richard C. Senger, Joining Materials and Processes in Electronic Packaging, at pages 577-619, and especially pages 580-583 of Donald P. Seraphim, Ronald Lasky, and Che-Yu Li, Principles of Electronic Packaging, previously incorporated herein by reference.
The TAB process involves bonding an IC chip to patterned metal on a polymer tape. Typically the polymer tape is a polyimide tape, although it may be polyester or poly perfluorocarbon, and the patterned metal is copper, for example a patterned copper film about 20 to about 40 microns thick. Adhesion of the copper to the polymer is obtained by plating the copper onto a multilayer of sputtered chromium and copper layers, each about 1 micron thick. This Cr-Cu multilayer provides a plating base for the Cu circuitization. The Cu circuitization is applied by vapor deposition or sputtering, and photolithographically patterned. Cu circuitization feature size is on the order of 50 microns.
An alternative TAB structure is formed by the spray deposition of polyimide. Thereafter the copper and the polyimide are patterned by etching with suitable etchants.
Bonding of the IC chip to the TAB copper leads is typically by thermal compression bonding or gold-tin liquid phase bonding to peripheral interconnections of the active device. The outer pads are soldered to the next level of packaging.
The surface circuitization is the power and signal interface between the package and the integrated circuit chips. Various methods are used to provide the bond between the integrated circuit chip leads and the surface circuitization. One method is the provision of gold surfaces, as thin film deposits and as "bumps", on the surface circuitization. These gold surfaces on selected regions of the copper circuitization can be utilized as solder pads, or as sites for thermal compression bonding.
The gold surfaces are typically "high purity" gold, also referred to as "soft" gold. High purity or soft gold is typically electroplated atop the copper surface circuitization from an electroplating solution having the composition shown in Table 1.
TABLE 1 ______________________________________ Typical Gold Electroplating Bath Formulation Component Concentration ______________________________________ KAu(CN).sub.2 20 g/L K.sub.2 HPO.sub.4 40 g/L KH.sub.2 PO.sub.4 10 g/L pH 7.0-7.5 ______________________________________
When the composition shown in Table 1 is used for electroplating a gold thin film onto copper surface circuitization on polyimide, as the polymeric reaction product of pyromellitic dianhydride and oxydianiline, there is a loss of adhesion between the copper circuitization and the polymeric substrate.
It is believed that this loss of adhesion arises because of electrochemical reactions in the polyimide during electrodeposition of the gold. The adhesion loss begins at the edge of the copper-polyimide interface and moves in toward the center of the copper-polyimide interface. The more severe the adhesion damage, the wider the area of edge adhesion loss will be. This adhesion loss is undesirable because it reduces the reliability of the circuitry.